• DocumentCode
    2675053
  • Title

    Accelerating tetrahedral interpolation with data-level and Thread-Level Parallel optimization

  • Author

    Ahn, Jaewoo ; Seong, Becksang ; Sung, Wonyong

  • Author_Institution
    Sch. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea
  • fYear
    2011
  • fDate
    June 30 2011-July 1 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The tetrahedral interpolation method for color space conversion consumes the longest time in the entire color management process. This makes it difficult to implement a purely software-based high-end image processing system. In this study, SIMD (Single Instruction Multiple Data) and GPGPU (General Purpose Graphics Processing Unit) based optimizations for tetrahedral interpolation are implemented. To exploit DLP (Data-Level Parallelism) with SIMD extensions, the program is restructured and conditional branches are removed so that inter-pixel parallelism is used for tetrahedron determination, while inter-output-channel parallelism is employed for the table lookup and weighted sum. TLP (Thread-Level Parallelism) is exploited with GPGPU by allocating different input pixels to each thread. Memory access cycle is minimized using constant memory for color lookup table. We conclude that both DLP and TLP optimization is essential for recent multi-core CPUs with wider SIMD registers and reducing the communication overhead between the host and the device is critical for TLP optimization with GPGPUs.
  • Keywords
    computer graphic equipment; coprocessors; interpolation; optimisation; parallel processing; table lookup; DLP; GPGPU; SIMD; accelerating tetrahedral interpolation; color management process; color space conversion; data level parallel optimization; data level parallelism; general purpose graphics processing unit; image processing system; inter output channel parallelism; interpixel parallelism; memory access cycle; single instruction multiple data; table lookup; thread level parallel optimization; Image color analysis; Indexes; Instruction sets; Interpolation; Optimization; Parallel processing; Pixel;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Circuits and Systems (ISSCS), 2011 10th International Symposium on
  • Conference_Location
    lasi
  • Print_ISBN
    978-1-61284-944-7
  • Type

    conf

  • DOI
    10.1109/ISSCS.2011.5978670
  • Filename
    5978670