A 600 nA, 0.7 ppm/°C CMOS voltage reference circuit without resistors

Author

Imbrea, Damian ; Cojan, Neculai ; Bonteanu, Gabriel

Author_Institution

Fac. of Electron., Telecommun. & Inf. Technol., Gh. Asachi Tech. Univ. of Iasi, Iasi, Romania

fYear

2011

fDate

June 30 2011-July 1 2011

Firstpage

1

Lastpage

4

Abstract

A new voltage reference circuit based only on MOS and vertical substrate PNP transistors is described. The circuit designed in 130 nm CMOS standard process operates in the temperature range [-40... +125] °C with supply voltages from 2.0 V to 3.0 V. It consumes 600 nA at 2.5 V and 27°C in the typical corner and occupies 0.0063 mm² area. The reference voltage is 1.0094 V ±35μV from 0°C to 100°C at 2.5V supply in the typical corner. A line sensitivity of 245 μV/V in the supply voltage range [2.25... 3.0] V is achieved. The power supply rejection ratio at 10 Hz is -71 dB.

Keywords

CMOS integrated circuits; power supplies to apparatus; reference circuits; CMOS voltage reference circuit; current 600 nA; line sensitivity; power supply rejection ratio; size 130 nm; temperature -40 degC to 125 degC; vertical substrate PNP transistors; voltage 2 V to 3 V; CMOS integrated circuits; MOSFETs; Noise; Photonic band gap; Resistors; Sensitivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Circuits and Systems (ISSCS), 2011 10th International Symposium on

Conference_Location

lasi

Print_ISBN

978-1-61284-944-7

Type

conf

DOI

10.1109/ISSCS.2011.5978739

Filename

5978739