Optimized packet pre-filtering for analysis of IP traffic on high-speed networks

Author

Lambruschini, P. ; Raggio, M. ; Bajpai, Rahul ; Sharma, Ashok

Author_Institution

Dept. of Naval, Electr., Electron. & Telecommun. Eng. (DITEN), Univ. of Genoa, Genoa, Italy

fYear

2012

fDate

18-21 Sept. 2012

Firstpage

1

Lastpage

4

Abstract

In this paper an efficient FPGA implementation of a packet pre-filtering algorithm based on Bloom filter is presented. In high speed link the traffic classification involves a very large amount of data per each packet processed (header and payload analysis). This leads to use hardware with high computational power and very expensive, in order to support requirement of real-time classification. Our system, reducing the data flow sent to the classifier allows a real-time classification with reduced hardware resources.

Keywords

IP networks; data structures; field programmable gate arrays; telecommunication traffic; Bloom filter; FPGA implementation; IP traffic analysis; computational power; hardware resources; header analysis; high speed networks; optimized packet prefiltering; packet prefiltering algorithm; payload analysis; real-time classification; traffic classification; Classification algorithms; Field programmable gate arrays; Filtering algorithms; Filtering theory; Hardware; IP networks; Real-time systems; FPGA implementation; IP traffic classification; packet pre-filtering;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals and Electronic Systems (ICSES), 2012 International Conference on

Conference_Location

Wroclaw

Print_ISBN

978-1-4673-1710-8

Electronic_ISBN

978-1-4673-1709-2

Type

conf

DOI

10.1109/ICSES.2012.6857541

Filename

6857541