High speed special function unit for graphics processing unit

A fixed-point ASIC design for high-speed, second-order, piecewise function approximation is presented. A Non-Uniform segmentation method based on Minimax approximation is used to get the interpolation coefficients. Non-Uniform segmentation, effectively, reduces the size of the coefficient table with a small area overhead for the address encoder. The proposed algorithm truncates the binary coefficients within the pre-al located error. Radix-eight Booth multipliers are used to reduce the number of partial products to, around one third of the traditional multiplication, hence speeding up the evaluation process. Very fast reduction trees with four-to-two compressors are used to reduce the number of the resulting partial products. Also, a new radix-eight sign template which reduces the overall area of the multipliers is proposed. Hybrid carry-look ahead, carry-ripple adders are, also, used. The design has been verified on FPGA Moreover, 45nm PDK is used to synthesize and layout the design. A maximum propagation delay of 5.251ns is achieved with a reduction of 19% in the total delay as compared to other traditional methods. A total chip area of 0.014mm² is also achieved.