SystemC/TLM semantics for heterogeneous system-on-chip validation

Author

Maraninchi, Florence ; Moy, Matthieu ; Cornet, Jérôme ; Maillet-Contoz, Laurent ; Helmstetter, Claude ; Traulsen, Claus

Author_Institution

VERIMAG Lab., CNRS, Grenoble

fYear

2008

fDate

22-25 June 2008

Firstpage

281

Lastpage

284

Abstract

SystemC has become a de facto standard for the system-level description of systems-on-a-chip. SystemC/TLM is a library dedicated to transaction level modeling. It allows to define a virtual prototype of a hardware platform, on which the embedded software can be tested. Applying formal validation techniques to SystemC descriptions of SoCs requires that the semantics of the language be formalized. The model of time and concurrency underlying the SystemC definition is intermediate between pure synchrony and pure asynchrony. We list the available solutions for the semantics of SystemC/TLM, and explain how to connect SystemC to existing formal validation tools.

Keywords

C language; electronic engineering computing; system-on-chip; virtual prototyping; SystemC descriptions; de facto standards; formal validation techniques; heterogeneous system-on-chip validation; system-level description; transaction level modeling; Circuit simulation; Embedded software; Hardware; Indium phosphide; Laboratories; Software libraries; Software prototyping; Software testing; System-on-a-chip; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on

Conference_Location

Montreal, QC

Print_ISBN

978-1-4244-2331-6

Electronic_ISBN

978-1-4244-2332-3

Type

conf

DOI

10.1109/NEWCAS.2008.4606376

Filename

4606376