• DocumentCode
    2680970
  • Title

    Formal verification of phase-locked loops using reachability analysis and continuization

  • Author

    Althoff, Matthias ; Yaldiz, Soner ; Rajhans, Akshay ; Li, Xin ; Krogh, Bruce H. ; Pileggi, Larry

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
  • fYear
    2011
  • fDate
    7-10 Nov. 2011
  • Firstpage
    659
  • Lastpage
    666
  • Abstract
    We present an approach for verifying locking of charge-pump phase-locked loops by performing reachability analysis on a behavioral model of the circuit. Bounded uncertain parameters in the behavioral model make it possible to represent all possible behaviors of more detailed models. The dynamics of the behavioral model is hybrid (i.e., discrete and continuous) due to the switching of charge pumps that drive the analog control circuits. A unique feature of phase-locked loops compared to most other hybrid systems is that they require thousands of switchings in the continuous dynamics to converge sufficiently close to a limit cycle. This makes reachability analysis a challenging task since switches in the dynamics are expensive to compute and result in conservative overapproximations. We solve this problem by overapproximating the effects of the switching conditions with uncertain parameters in linear continuous models, a method we call continuization. Using efficient reachability algorithms for discrete-time linear systems, locking is verified over the complete range of possible initial states of a charge-pump PLL designed in 32nm CMOS SOI technology in comparable time required for Monte Carlo simulations of the same behavioral model.
  • Keywords
    CMOS integrated circuits; Monte Carlo methods; charge pump circuits; electronic engineering computing; formal verification; phase locked loops; silicon-on-insulator; CMOS SOI technology; Monte Carlo simulations; analog control circuits; charge-pump PLL; circuit behavioral model; conservative overapproximations; continuization; discrete-time linear systems; formal verification; linear continuous models; phase-locked loops; reachability analysis; size 32 nm; switching conditions; Charge pumps; Computational modeling; Integrated circuit modeling; Phase frequency detector; Phase locked loops; Reachability analysis; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4577-1399-6
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2011.6105400
  • Filename
    6105400