Memory System Design for a Multi-core Processor

Author

Guo, Jianjun ; Lai, Mingche ; Pang, Zhengyuan ; Huang, Libo ; Chen, Fangyuan ; Dai, Kui ; Wang, Zhiying

Author_Institution

Sch. of Comput., Nat. Univ. of Defense Technol., Changsha

fYear

2008

fDate

4-7 March 2008

Firstpage

601

Lastpage

606

Abstract

Multi-core processor has become hot research area recently. Cache results in high cost to maintain consistency between different data copies in multi-core processor especially in many-core processor. A hybrid memory architecture is proposed for the specific multi-core processor which uses cache for instruction while local storage for data. This paper focuses on the design and optimization of the proposed memory architecture. L1 instruction cache, local data storage, DMA engine, L2 cache and MMU is designed and optimized. L2 cache replacement strategy is studied to reduce the total miss cost.

Keywords

cache storage; memory architecture; DMA engine; L1 instruction cache; L2 cache; MMU; hybrid memory architecture; local data storage; many-core processor; memory system design; multicore processor; Computer architecture; Costs; Design optimization; Hardware; Memory architecture; Multicore processing; Parallel processing; Processor scheduling; Registers; Sockets;

fLanguage

English

Publisher

ieee

Conference_Titel

Complex, Intelligent and Software Intensive Systems, 2008. CISIS 2008. International Conference on

Conference_Location

Barcelona

Print_ISBN

978-0-7695-3109-0

Type

conf

DOI

10.1109/CISIS.2008.39

Filename

4606741