Energy efficiency in dynamically reconfigurable SoC for data-parallel applications

Power consumption is becoming a concern in programmable logic design as the size and performance of modern FPGAs increase. Data-parallel applications can work on different parallelism level so as to achieve different performance. This paper presents an investigation into the best parallelism degree-operating frequency tradeoff in order to find the optimum number of instances for each parallelizable task with adequate operating frequency minimizing energy and power for a given throughput constraint. Significant optimization can be achieved not only in power and energy but also in terms of adaptation to environment conditions such as variable data rate and scalability in the multimedia applications.