A Delay Locked Loop for fine time base generation in a positron emission tomography scanner

Author

Abidi, Mouadh ; Calliste, Konin Koua ; Kanoun, Moez ; Panier, Sylvain ; Arpin, Louis ; Tétraul, Marc-André ; Pratte, Jean- François ; Fontaine, Réjean

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. de Sherbrooke, Sherbrooke, QC, Canada

fYear

2010

fDate

23-25 March 2010

Firstpage

1

Lastpage

4

Abstract

In this paper, an analog Delay Locked Loop with fixed latency of one clock cycle is proposed. It was implemented with differential delay cells in order to reduce noise, and based on a precise dynamic phase comparator. With a 1.8 V supply and a 100 MHz input clock, the DLL consumes 3.4 mW and the measured jitter is 3.9 ps rms. It was implemented on a 0.18 μm TSMC CMOS technology and occupies an active area of 0.0022 mm².

Keywords

CMOS integrated circuits; clocks; delay lock loops; positron emission tomography; TSMC CMOS technology; delay locked loop; differential delay cells; dynamic phase comparator; fine time base generation; positron emission tomography scanner; Bandwidth; Charge pumps; Clocks; Delay effects; Frequency; Low pass filters; Partial discharges; Positron emission tomography; Transfer functions; Voltage control; CMOS; DLL; charge pump; delay; phase comparator;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on

Conference_Location

Hammamet

Print_ISBN

978-1-4244-6338-1

Type

conf

DOI

10.1109/DTIS.2010.5487578

Filename

5487578