DocumentCode
2684012
Title
Effect of gate bias on ESD characteristics in NMOS device
Author
He, Yujuan ; En, Yunfei ; Luo, Hongwei ; Xiao, Qingzhong
Author_Institution
Sci. & Technol. on Reliability Phys. & Applic. of Electr. Component Lab., Guangzhou, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
360
Lastpage
362
Abstract
Oxide trapped charges which were produced in oxide area of MOSFET in the process of using can cause ESD characteristic changed. So the gate forced given bias to Simulate oxide trapped charges. In this paper, TLP test method was used to study the ESD parameters of NMOSFET with various gate biases. It was indicated that the threshold voltage Vt1 and secondary breakdown current It2 first increased and then decreased with the gate voltage increasing, but the maintained Voltage Vsp essentially unchanged.
Keywords
MOS integrated circuits; MOSFET; electrostatic discharge; ESD characteristics; NMOS device; NMOSFET; TLP test method; gate bias; oxide trapped charges; Breakdown voltage; Electrostatic discharges; Logic gates; MOSFET circuits; Materials; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Packaging Materials (APM), 2011 International Symposium on
Conference_Location
Xiamen
ISSN
1550-5723
Print_ISBN
978-1-4673-0148-0
Type
conf
DOI
10.1109/ISAPM.2011.6105756
Filename
6105756
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