Distributed crossbar schedulers

The goal of this work is to enable distributed (multi-chip) implementations of iterative matching algorithms for crossbar-based packet switches, as opposed to the traditional monolithic (single-chip) ones. The practical motivation for this effort is the design and implementation in FPGAs of a scheduler for a 64-port optical crossbar switch. Sizing experiments show that the scheduler logic must be distributed over multiple devices, which introduces a number of new challenges. Most importantly, the physical distances introduce latencies that exceed the timing requirements, and the separation of logical units prevents shared access to status information. We consider three levels of distribution, and present techniques to mitigate the consequences of specific distribution levels. The performance results obtained via simulation show that, using these methods, a distributed scheduler can achieve a performance close to that of a monolithic scheduler, even with large internal latencies