DocumentCode
2686271
Title
Scalable two-stage Clos-network switch and module-first matching
Author
Rojas-Cessa, Roberto ; Lin, Chuan-Bi
Author_Institution
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ
fYear
0
fDate
0-0 0
Abstract
Clos-network switches were proposed as a scalable architecture for the implementation of large-capacity circuit switches. In packet switching, the three-stage Clos-network architecture uses small switches as modules to assemble a switch with large number of ports or aggregated ports with high data rates. However, the configuration complexity of packet Clos-network switches is high as port matching and path routing must be performed. In the majority of the existing schemes, the configuration process performs routing after port-matching is achieved, and thus making port matching expensive in hardware and time complexity for a large number of ports. Here, we reduce the configuration complexity by performing routing first and port matching afterwards in a three-stage Clos-network switch. This approach applies the reduction concept of Clos networks to the matching process. This approach results in a feasible size of schedulers for up to Exabit-capacity switches, an independent configuration of the middle stage modules from port matches, a reduction of the matching communication overhead between different stages, and a release of the switching function to the last-stage modules in a three-stage switch. By using this novel matching scheme, we show that the number of stages of a Clos-network switch can be reduced to two, and we call this the two-stage Clos-network packet switch
Keywords
multistage interconnection networks; packet switching; telecommunication network routing; Exabit-capacity switch; module-first matching; packet switching; path routing; scalable architecture; two-stage Clos-network switch; Assembly; Asynchronous transfer mode; Communication switching; Fabrics; Hardware; Impedance matching; Packet switching; Routing; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Switching and Routing, 2006 Workshop on
Conference_Location
Poznan
Print_ISBN
0-7803-9569-7
Type
conf
DOI
10.1109/HPSR.2006.1709725
Filename
1709725
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