Channelized receiver platform of SDR based on FPGAs

Author

Ren Guanghui ; Zhao Yaqin ; Wu Zhilu ; Gu Xuemai

Author_Institution

Harbin Inst. of Technol., China

Volume

2

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

840

Abstract

In this paper, a channelized receiver platform of software defined radio is developed which is mainly to realize wideband quadrature digitization, modulation classification and demodulation exploiting A/D converters. FPGAs with the combination of programmable DSPs. The front-end of researched receiver based on polyphase filter quadrature digitization processors, where digitization takes place at intermediate frequencies (IF), adopts a wideband design with a bandwidth of up to 100MHz and a centered carrier frequency of up to 250MHz. The low-complexity high-speed digital IF signal processing is carried out with CORDIC algorithm on FPGAs, then to realize the recognition of several modulation schemes such as 2ASK, 4ASK, 2PSK, 4PSK, 2FSK, 4FSK, 16QAM to implement communication protocols fairly flexibly.

Keywords

digital signal processing chips; field programmable gate arrays; high-speed integrated circuits; integrated circuit design; radio receivers; software radio; 100 MHz; 250 MHz; A-D converters; CORDIC algorithm; FPGA; SDR; channelized receiver platform; communication protocols; field programmable gate array; high-speed digital IF signal processing; low-complexity IF signal processing; modulation classification; modulation schemes; polyphase filter quadrature digitization processors; programmable DSP; software defined radio; wideband design; wideband quadrature digitization;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277341

Filename

1277341