DocumentCode
2686488
Title
On accommodating particular analog system models with VHDL
Author
Popescu, Gabriel Stefan
Author_Institution
Tech. Univ. of Iasi, Romania
fYear
2000
fDate
2000
Firstpage
77
Lastpage
82
Abstract
In this paper the problem of accommodating particular analog system models, with emphasis on interconnection representation, with discrete event simulators, and particularly with VHDL circuit descriptions, is discussed and a solution is proposed. The results can be successfully used for VHDL modeling and simulation, but they are implementation independent
Keywords
VLSI; circuit simulation; digital integrated circuits; discrete event simulation; hardware description languages; integrated circuit interconnections; integrated circuit modelling; VHDL circuit descriptions; VHDL modelling; VHDL simulation; analog system models; digital ICs; discrete event simulators; interconnection representation; Circuit simulation; Digital integrated circuits; Discrete event simulation; Distributed parameter systems; Equations; Hardware design languages; Integrated circuit interconnections; LAN interconnection; Linear approximation; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Behavioral Modeling and Simulation, 2000. Proceedings. 2000 IEEE/ACM International Workshop on
Conference_Location
Orlando, FL
Print_ISBN
0-7695-0893-6
Type
conf
DOI
10.1109/BMAS.2000.888368
Filename
888368
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