Practical implementation of blind equalization, carrier recovery and timing recovery for QAM cable receiver chip

This paper is concerned with the system level design of quadrature amplitude modulation (QAM) cable receiver chip for cable HDTV application. We introduce a receiver structure with joint blind decision feedback equalizer (DFE) loop, timing recovery loop, carrier recovery loop and AGC loop. The architecture of blind dual mode DFE, with constant modulus algorithm (CMA) initialization block, dual mode feed-forward filter and feedback filter, operates in the passband so that equalizer can be adjusted completely independent of carrier phase. For VLSI realization, the hybrid form, one of pipelined structure without introducing extra latency is applied to the DTE. The all digital synchronization loops such as timing recovery are also described. The timing recovery architecture features with recirculating decimator for variable rate interpolation that allows it operate at any user specified symbol rate from 875kbaud to 7Mbaud. The SPW HDS™ simulation and Xilinx VirtexTM-II 3000 FPGA verification confirm that proposed scheme is robust against non-impulse noise, multi-paths and carrier error such as frequency offset, phase offset and phase jitter.