VLSI architecture for multi-resolution three step search algorithm

In this paper a modification in the three step search (TSS) block matching algorithm using the concept of multi-resolution has been proposed. It has been experimented that the proposed algorithm outperforms the TSS algorithm in most of the cases. Based on the proposed algorithm, VLSI architecture for the motion estimation chip suitable in video compression is presented. The architecture based on the proposed algorithm requires significantly lesser number of gate counts and simple control overhead compared to the existing architectures in the same domain. Moreover, it requires lesser amount of data access with reduced switching activity and thus gives an effective solution for power conscious portable video applications.