H.264 codec system-on-chip design and verification

We designed a SoC/ASIC to implement the low power, high performance H.264 encoder and decoder with a 32-bit RISC CPU on a single chip. We used the system-level modeling technique to develop the H.264 codec and high-speed RISC microprocessor cores, and adopted the transaction-level based verification technique to do the automatic self-checking, regression testing for the design. The SoC runs the H.264 codec in hardware. It incorporated standard peripheral interfaces, such as UART, USB, 100/10 Mbps Ethernet, IEEE 1394, ATAPI and SVGA. It supports embedded real-time OS for PDA and wireless applications. It is implemental for complicated Linux operating systems used for personal video recorder, DVD recorder, game and set top boxes, digital camcorders, video conferencing kit, and network computers.