• DocumentCode
    2687051
  • Title

    A 10-bit 40MSPS pipeline analog-to-digital converter

  • Author

    Jun, Cai ; Feng, Ran ; Meihua, Xu

  • Author_Institution
    Key Lab. of Adv. Display & Syst. Applic., Shanghai Univ., Shanghai
  • fYear
    2008
  • fDate
    28-31 July 2008
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A 40 MSample/s, 10-bit, 3.3V pipeline ADC is presented. In order to achieve very low power consumption, it employs a high bandwidth low-power amplifiers technique and a low power low offset dynamic comparators technique. The ADC is designed in 0.35 mum CMOS technology and occupies 1.2*0.8 mm2.
  • Keywords
    CMOS integrated circuits; amplifiers; analogue-digital conversion; comparators (circuits); low-power electronics; CMOS technology; dynamic comparators; high bandwidth low-power amplifiers; low power consumption; pipeline analog-to-digital converter; size 0.35 mum; voltage 3.3 V; word length 10 bit; Analog-digital conversion; Bandwidth; CMOS technology; Circuits; Energy consumption; High power amplifiers; Pipelines; Power dissipation; Sampling methods; Signal resolution;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-2739-0
  • Electronic_ISBN
    978-1-4244-2740-6
  • Type

    conf

  • DOI
    10.1109/ICEPT.2008.4607034
  • Filename
    4607034
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2687051