A 3.3 V-only 16 Mb DINOR flash memory

Author

Kobayashi, S. ; Mihara, Mitsuharu ; Miyawaki, Y. ; Ishii, M. ; Futatsuya, T. ; Hosogane, A. ; Ohba, A. ; Terada, Yuki ; Ajika, N. ; Kunori, Yuta ; Yuzuriha, K. ; Hatanaka, M. ; Miyoshi, Hidenori ; Yoshihara, Tatsuhiko ; Uji, Y. ; Matsuo, Akihiko ; Taniguc

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

122

Lastpage

123

Abstract

A 3.3 V only, block erasable 16 Mb divided bit-line NOR-DINOR flash memory has 47 ns random access time and 1 MB programming throughput. Power consumption in program operation is 60 mW. This memory is fabricated using a 0.5 /spl mu/m design-rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4/spl times/1.35 /spl mu/m/sup 2/. 256B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.

Keywords

CMOS memory circuits; 0.5 micron; 16 Mbit; 3.3 V; 47 ns; 60 mW; Al-Si; DINOR flash memory; NOR-DINOR type; block erasable memory; divided bit-line; double-layer Al; efficient charge pump; high speed operation; low power consumption; optimized source/drain memory cell structure; page buffer; triple-layer polysilicon; triple-well CMOS; Charge pumps; Circuits; Diodes; Energy consumption; Flash memory; Latches; P-n junctions; Parasitic capacitance; Threshold voltage; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535457

Filename

535457