DocumentCode
2687922
Title
Physical implementation and test of energy recovery circuit
Author
Zhang Sheng ; Zhou Runde
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
1205
Abstract
This paper presents a new structure of energy recovery logic named improved energy recovery logic (IERL) and discusses the physical implementation issues. A feasible test schemes for function verification and power measurement of energy recovery logic circuit is proposed and put in practice. The test results verified the proper function of IERL 2-bit full adder (FA) circuit and the low power performance. When the power clock is set at 2MHz, the average power consumption of IERL 2-bit FA is 66% of its CMOS counterpart.
Keywords
adders; logic circuits; logic testing; low-power electronics; power measurement; 2 MHz; CMOS; IERL; energy recovery circuit; feasible test schemes; full adder circuit; function verification; improved energy recovery logic; low power performance; physical implementation; power clock; power measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277430
Filename
1277430
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