DocumentCode
2688385
Title
WAVETM technology for wafer level packaging of ICs
Author
Fjelstad, Joseph
Author_Institution
Tessera Inc., San Jose, CA, USA
fYear
1998
fDate
8-10 Dec 1998
Firstpage
214
Lastpage
218
Abstract
Wide area vertical expansion (WAVE) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Based on concepts that allow for the mass assembly and production of compliant packages on the wafer, this important new technology is described in terms of the process and device, and the implications and future directions of the technology are examined
Keywords
assembling; integrated circuit interconnections; integrated circuit manufacture; integrated circuit packaging; technological forecasting; IC interconnection; WAVE technology; compliant packages; cost effectiveness; mass assembly; mass production; wafer level IC packaging; wide area vertical expansion technology; Assembly; Chip scale packaging; Electron tubes; Electronics packaging; Integrated circuit packaging; Semiconductor device packaging; Silicon; Substrates; Transistors; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 1998. Proceedings of 2nd
Print_ISBN
0-7803-5141-X
Type
conf
DOI
10.1109/EPTC.1998.756004
Filename
756004
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