High Throughput, Pipelined Implementation of AES on FPGA

The FPGA-based high throughput 128 bits AES cipher processor is proposed in this paper. We present an equivalent pipelined AES architecture working on CTR mode to provide the highest throughput up to date through inserting some registers in appropriate points making the delay shortest, when implementing the byte transformation in one clock period. The equivalent pipelined architecture does not change the data stream direction but change the inner process order in round transformation. Xilinx Foundation ISETM 10.1 FPGA design tool is used in the synthesis of the design. And the throughput of 73.737 Gbps, clock frequency of 576.07 MHz and resource efficiency of 3.21 Mbps/LUT are provided by the proposed equivalent pipelined AES architecture. The proposed design reach higher throughput than the other designs up to date, and its resource efficiency is also very high.