Short channel vertical transistors with excellent saturation characteristics

The use of a vertical thin film transistor (VTFT) topology in the flat panel active matrix array, opens up a plethora of new high performance applications. The VTFT is small in footprint by virtue of its stacked layer configuration, in which channel lengths can be conveniently scaled down to nanometer regime without having to resort to photolithography as would otherwise be needed when scaling lateral TFTs. More importantly, the VTFT is also fully compatible to the materials and processes used in flat panel technology, takes making it amenable to large area scaling. In the VTFT, the source and drain electrodes are vertically stacked and separated by an intermediate insulator layer. The channel is formed on the vertical sidewall of the source/insulator/drain stack. Since the thickness of intermediate insulator layer defines the channel length, this can now be accurately controlled at the nanometer scale via the thickness of the insulator layer. While nanoscale channel length VTFTs in amorphous silicon (a-Si) have been demonstrated previously, one of the biggest issues was the lack of good saturation behavior at high drain voltages, which made reduction of the gate dielectric thickness mandatory. However, reducing the gate dielectric thickness leads to high gate leakage and early dielectric breakdown. This presentation is on short-channel VTFTs with excellent saturation characteristics, achieved by an ultra-thin silicon nitride (SiN_x) gate dielectric using plasma-enhanced chemical vapor deposition (PECVD).