Distributed arithmetic-based architectures for high speed IIR filter design

Dedicated VLSI has been considered as an effective method to realize the DSP algorithms which require massive amount of computations. To speed up the computing, parallel processing and pipelining techniques are often employed. However, for those recursive algorithms where the available computing concurrency is very limited, these design tactics do not help. Previous results suggest a Look-ahead transform method applied to the algorithm first to create the parallelism at the cost of drastically increased hardware complexity. In this paper, we present a Distributed Arithmetic based scheme to solve the problem without resorting to the expensive look-ahead methods. In contrast to the conventional “bit-parallel word-serial” computing paradigm, the new scheme features a “bit-serial word-parallel” approach. In this scheme, instead of waiting the entire data word available from the previous recursion, current recursion´s computation can start as soon as the LSB from the previous recursion is obtained. This means the initiation interval between two successive input data is reduced from the delay of computing one word to the delay of computing one bit. To illustrate the merits of this new scheme, we present a DA based VLSI design for an IIR filter. The design is implemented using a 0.8 μm SPDM technology and can achieve high throughput rate operation for real time applications