Garp: a MIPS processor with a reconfigurable coprocessor

Author

Hauser, John R. ; Wawrzynek, John

Author_Institution

California Univ., Berkeley, CA, USA

fYear

1997

fDate

16-18 Apr 1997

Firstpage

12

Lastpage

21

Abstract

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications

Keywords

coprocessors; field programmable gate arrays; general purpose computers; instruction sets; microprocessor chips; performance evaluation; reconfigurable architectures; FPGA; Garp Architecture; MIPS processor; UltraSPARC; field programmable gate arrays; general-purpose computing; performance; prototype software environment; reconfigurable coprocessor; reconfigurable machines; speedups; Application software; Circuits; Computer architecture; Coprocessors; Field programmable gate arrays; Hardware; Reconfigurable logic; Software performance; Software prototyping; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8159-4

Type

conf

DOI

10.1109/FPGA.1997.624600

Filename

624600