A 300 MHz 64 b quad-issue CMOS RISC microprocessor

Author

Bowhill, W.J. ; Allmon, R.L. ; Bell, S.L. ; Cooper, E.M. ; Donchin, D.R. ; Edmondson, J.H. ; Fischer, T.C. ; Gronowski, P.E. ; Jain, A.K. ; Kroesen, P.L. ; Loughlin, B.J. ; Preston, R.P. ; Rubinfeld, P.I. ; Smith, M.J. ; Thierauf, S.C. ; Wolrich, G.M.

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

182

Lastpage

183

Abstract

This quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS/600 MFLOPS (peak) performance. The 16.5/spl times/18.1 mm/sup 2/ die contains 9.3 M transistors. It is built in a 3.3 V 4-layer metal, 0.5 /spl mu/m CMOS process. The upper metal layers are used primarily for power, clock, and global bus distribution. The chip is packaged in a 499-pin ceramic IPGA with 205 pins dedicated to VDD/VSS. The package includes a copper tungsten intrusive slug that provides a low thermal resistance between the die and a detachable heat sink. The chip is air cooled and dissipates 50 W at 300 MHz. 160 nF of on-chip decoupling capacitance controls power-supply noise.

Keywords

CMOS digital integrated circuits; VLSI; microprocessor chips; reduced instruction set computing; 0.5 micron; 1200 MIPS; 160 nF; 3.3 V; 300 MHz; 4-layer metal CMOS process; 50 W; 600 MFLOPS; 64 bit; Alpha architecture; RISC microprocessor; air cooling; ceramic IPGA; custom VLSI implementation; detachable heat sink; onchip decoupling capacitance; quad-issue CMOS microprocessor; CMOS process; Ceramics; Clocks; Microprocessors; Packaging; Pins; Reduced instruction set computing; Thermal resistance; Variable structure systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535514

Filename

535514