Electrical design techniques for high-speed circuit boards

Novel techniques are proposed for high-speed circuit board design. They use two layout simulators and are expected to improve the design quality and to shorten the design cycle. The prelayout simulator generates design rule formulas representing the relationship between physical dimensions and electrical properties such as delay, crosstalk, and reflection. An accurate formula for multiple saturation crosstalk induced by many long parallel segments of an active line is developed. The postlayout simulator generates equivalent circuit descriptions for routed wirings and displays their simulated reflection and crosstalk waveforms. The method of suppressing nodes between two segments of a line on the same layer is found to be useful for decreasing simulation time.<>