Degradation of III–V inversion-type enhancement-mode MOSFETs

Author

Wrachien, N. ; Cester, A. ; Zanoni, E. ; Meneghesso, G. ; Wu, Y.Q. ; Ye, P.D.

Author_Institution

Dept. of Inf. Eng., Univ. of Padova, Padova, Italy

fYear

2010

fDate

2-6 May 2010

Firstpage

536

Lastpage

542

Abstract

We performed gate ramp voltage stress on III-V InGaAs based MOSFETs. Stress induces trapped charge and it also leads to interface trap generation, which has detrimental effects on the subthreshold slope and on the transconductance. At high electric fields, before the hard breakdown, a very low-frequency high-current random telegraph noise appears at the gate, which seems to be not correlated with the soft breakdowns commonly observed in other devices.

Keywords

III-V semiconductors; MOSFET; electric field effects; gallium compounds; indium compounds; semiconductor device breakdown; semiconductor device noise; semiconductor device reliability; III-V inversion-type enhancement-mode MOSFET; InGaAs; dielectric breakdown; electric fields; gate ramp voltage stress; interface trap generation; low-frequency high-current random telegraph noise; semiconductor device reliability; soft breakdowns; stress induced trapped charge; subthreshold slope; transconductance; Degradation; Electric breakdown; III-V semiconductor materials; Indium gallium arsenide; Low-frequency noise; MOSFETs; Stress; Telegraphy; Transconductance; Voltage; III–V MOSFET; reliability; stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2010 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4244-5430-3

Type

conf

DOI

10.1109/IRPS.2010.5488775

Filename

5488775