Verification of in-order execution in pipelined processors

Due to advances in semiconductor technologies and the increasing demand on high performance, pipelined processors have been widely used even in low- to mid-end embedded systems. Customization of the pipeline structure to a specific application permits efficient implementation of the embedded systems. In the design of pipelined processors, functional verification is one of the most critical issues, and formal or semiformal methods are considered as promising approaches to it. In this paper we present a finite state machine (FSM)-based modeling of pipelined processors with in-order execution. Based on the FSM-based modeling, we propose an efficient approach to formally verifying the correctness of in-order execution in the pipeline. We also report oar preliminary experimental results