A multiple configuration 1.2 micron 64 K SRAM fabricated on SIMOX substrates with laser link redundancy

Summary form only given. A high-speed, radiation-hardened, architecturally configurable (single metal mask) 64 K SRAM is discussed. Two configurations, the 64 K×1 and 8 K×8, have been built and 100% functional dies have been tested. Typical measured chip enable access times are under 35 nS for the 64 K×1 version, with minimum write times of 15 ns. The process features 1.2-μm minimum geometries and dual-level metal, single-level polysilicon interconnect. First metal pitch is 3.6 μm, second metal pitch is 3.8 μm, and polysilicon pitch is 2.6 μm. 1.2-μm contacts and 1.8-μm vias are utilized for interlayer connections. A thin 0.4-μm epitaxial layer is grown on a SIMOX (separation by implantation of oxygen) substrate allowing for fully bottomed source and drain areas. Lateral isolation is provided by vertical trenches. Nominal gate oxide thickness is 225 A. Laser opened second metal layer links are used to implement redundancy capability for yield improvement