Investigation on the effective immunity to process induced line-edge roughness in silicon nanowire MOSFETs

The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great potential in high-performance nano-electronics applications. However, line-edge roughness (LER) induced by lithography and etching processes has become a critical concern for decananometer MOSFETs, because it does not scale accordingly with line widths. Especially, the LER of nanowires, which contains two degrees of freedom rather than one in the traditional planar devices, may have different and intriguing effect on SNWTs. Therefore, performance variation of SNWTs induced by nanowire-LER may become a great challenge to scalability and stability of SNWT-based ICs, where 2-D geometrical fluctuation becomes an even more serious problem in nano-scale. Yet, only few preliminary studies on such impact have been reported. In this paper, a full 3-D statistical investigation is performed, based on the measured LER from SEM images, to estimate the impact of nanowire-LER on SNWTs, including both DC and analog/RF performance. The results can provide guidelines for process optimization as well as robust design of SNWT-based circuits.