A CMOS/SOS process for high reliability, radiation hard, high speed memory and logic IC´s

A brief description is given of a low power, high speed, radiation hardened CMOS/SOS 64-K word by 1-b static RAM designed and fabricated with 2.0 μm polysilicon and double level metal technology. The main RAM circuit design consists of an address transition detector, a bit-line prechange circuit, a multi-state row decoder, and a highly sensitive double-stage sense amplifier. The bit-line and bit-line-bar signals are normally precharged to (Vdd-Vthn) or approximately 3.5 V. The differential signals from the bit line pair are connected to the first-stage sense amplifier which feeds the output to the second-stage sense amplifier. The second-stage sense amplifier provides the current needed to drive the long, main data-line connected directly to the output buffer. The high sensing gain of the current mirror sense amplifier, which senses less than 150 mV, enables the device to achieve 35-ns fast access time