A 10b 3MSample/s CMOS cyclic ADC

Author

Kitagawa, A. ; Kokubo, M. ; Tsukada, T. ; Matsuura, T. ; Hotta, M. ; Maio, K. ; Yamamoto, E. ; Imaizumi, E.

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

fYear

1995

fDate

15-17 Feb. 1995

Firstpage

280

Lastpage

281

Abstract

This low-power, small-area, 10 b 3 MSample/s (0.33 /spl mu/s) CMOS on-chip ADC uses an improved recursive subranging approach. A multi-path cyclic-conversion architecture, an implementation of a recursive subranging architecture, is proposed to further reduce the power by reducing the required circuit speed. As a result, this ADC achieves compatibility between the low-power and small-area requirements. For on-chip system application, a module that includes bus interface circuitry and buffer amplifiers for the reference-voltage generators is implemented in addition to the 10 b 3 MSample/s ADC.

Keywords

CMOS integrated circuits; analogue-digital conversion; 0.33 mus; 10 bit; CMOS cyclic ADC; buffer amplifiers; bus interface circuitry; circuit speed; low-power small-area on-chip ADC; module; multi-path cyclic-conversion; recursive subranging architecture; reference-voltage generators; Area measurement; CMOS process; Energy consumption; Power measurement; Power supplies; Solid state circuits; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-2495-1

Type

conf

DOI

10.1109/ISSCC.1995.535556

Filename

535556