Phase shift accumulation method for timing characterization

This paper explains the creation of new approach of propagation delay measurement in nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor´s parameters. Physical implementation of phase error accumulation method (PHEAM) can be easy integrated at the same chip as close as possible to the device under test (DUT). It was implemented as digital IP core for semiconductor manufacturing process (0.11μm, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.