• DocumentCode
    2702790
  • Title

    At-speed test on the QorIQTM P2020 platform

  • Author

    Renfrew, Colin D. ; Booth, Brian ; Latawa, Shweta ; Woltenberg, Rick ; Pyron, Carol

  • Author_Institution
    Freescale Semicond., Inc., Austin, TX, USA
  • fYear
    2009
  • fDate
    1-6 Nov. 2009
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    This paper describes how at-speed testing for delay faults was achieved on the P2020 QorIQ device. Modifications to the scan clocking architecture were made over previous designs in order to facilitate at-speed testing and improve overall test coverage. A methodology for ATPG was derived for this enhanced architecture and applied to the device. The design and implementation will be presented in this paper, along with results from ATPG and silicon.
  • Keywords
    automatic test pattern generation; clocks; delays; electrical faults; elemental semiconductors; fault diagnosis; integrated circuit testing; silicon; system-on-chip; ATPG; QorIQ P2020 platform; Si; at-speed test; delay fault testing; scan clocking architecture; silicon device; Automatic test pattern generation; Clocks; Delay; Fault detection; Lab-on-a-chip; Performance evaluation; Runtime; Semiconductor device testing; Silicon; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2009. ITC 2009. International
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4244-4868-5
  • Electronic_ISBN
    978-1-4244-4867-8
  • Type

    conf

  • DOI
    10.1109/TEST.2009.5355588
  • Filename
    5355588
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2702790