A test vector ordering technique for switching activity reduction during test operation

Author

Girard, P. ; Guiller, L. ; Landrault, C. ; Pravossoudovitch, S.

Author_Institution

Lab. d´´Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

fYear

1999

fDate

4-6 Mar 1999

Firstpage

24

Lastpage

27

Abstract

This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on the reordering of test vectors of a given test sequence to minimize the average and peak power dissipation during test operation. For this purpose, the proposed technique reduces the internal switching activity by lowering the transition density at circuit inputs. The technique considers combinational or full scan sequential circuits and do not modify the initial fault coverage. Results of experiments show reductions of the switching activity ranging from 11% to 66% during external test application

Keywords

VLSI; automatic test pattern generation; combinational circuits; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; VLSI integrated circuits; average power dissipation; combinational circuits; full scan sequential circuits; internal switching activity; peak power dissipation; power ratings; switching activity reduction; test operation; test vector ordering technique; transition density reduction; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Integrated circuit testing; Nondestructive testing; Power dissipation; Robots; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757369

Filename

757369