No-race charge-recycling differential logic (NCDL)

Author

Yoo, Seung-Moon ; Kang, Sung-Mo

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1999

fDate

4-6 Mar 1999

Firstpage

202

Lastpage

205

Abstract

This paper describes no-race charge-recycling differential logic (NCDL) which realizes low power computation with less sensitivity to input signal skews. Performance comparison with previous charge recycling logics is shown for a 2-input NAND logic. NCDL operates in push-pull mode and achieves about 35% improvement in power-delay product over full swing differential logic without the pre-evaluation problems. Thus, it shows increased effectiveness for the implementation of random logic with input signals arriving in an arbitrary sequence

Keywords

MOS logic circuits; NAND circuits; VLSI; circuit simulation; logic simulation; low-power electronics; arbitrary sequence; input signal skews; input signals; low power computation; no-race charge-recycling differential logic; power-delay product; push-pull mode; random logic; two-input NAND logic; Circuit synthesis; Energy consumption; Logic circuits; Logic design; Logic devices; MOSFETs; Power engineering computing; Recycling; Threshold voltage; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757410

Filename

757410

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2703873