DocumentCode
2703985
Title
An asynchronous router for multiple service levels networks on chip
Author
Rostislav, Dobkin ; Vishnyakov, Victoria ; Friedman, Eyal ; Ginosar, Ran
Author_Institution
VLSI Syst. Res. Center, Technion-Israel Inst. of Technol., Haifa, Israel
fYear
2005
fDate
14-16 March 2005
Firstpage
44
Lastpage
53
Abstract
Networks on chip that can guarantee quality of service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementations, to eliminate the need for synchronization when crossing clock domains. An asynchronous multi-service level QNoC router is investigated. It comprises multiple interconnected input and output ports, and arbitration mechanisms that resolve any output port and service level conflicts. Buffering and credit based transport are enabled, enhancing throughput. A synchronous and an asynchronous router have been designed, and their performance is compared. The asynchronous router requires less area and enables a higher data rate.
Keywords
asynchronous circuits; buffer circuits; multiprocessor interconnection networks; quality of service; system-on-chip; telecommunication network routing; GALS SoC; QNoC; QoS guarantees; arbitration mechanisms; asynchronous router; buffering; credit based transport; multiple interconnected input/output ports; multiple service level NoC; networks on chip; preemptive routing; quality of service; service level conflict resolution; synchronous routers; wormhole routing; Asynchronous circuits; Clocks; Delay; Frequency synchronization; Integrated circuit interconnections; LAN interconnection; Network-on-a-chip; Power system interconnection; Quality of service; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on
ISSN
1522-8681
Print_ISBN
0-7695-2305-6
Type
conf
DOI
10.1109/ASYNC.2005.11
Filename
1402045
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