A novel low power low phase-noise PLL architecture for wireless transceivers

Author

Hafez, Amr N. ; Elmasry, M.I.

Author_Institution

VLSI Res. Group, Waterloo Univ., Ont., Canada

fYear

1999

fDate

4-6 Mar 1999

Firstpage

306

Lastpage

309

Abstract

A sample-and-hold stage placed in the feedback path of a PLL frequency synthesizer reduces the division ratio, and hence the phase-detector phase-noise, without the need of multiple loops, when used in conjunction with a DDS, this architecture simplifies the DDS design leading to a low-power architecture. Furthermore, this architecture allows for a large loop bandwidth thus suppressing the VCO phase-noise. The advantages of this architecture are highlighted and system- and circuit-level simulations presented

Keywords

CMOS integrated circuits; VLSI; circuit feedback; direct digital synthesis; low-power electronics; phase locked loops; phase noise; transceivers; DDS design; PLL frequency synthesizer; VCO phase-noise suppression; circuit-level simulations; division ratio reduction; feedback path; loop bandwidth; low phase-noise PLL architecture; low power PLL architecture; phase-detector phase-noise; sample/hold stage; system-level simulations; wireless transceivers; Bandwidth; Channel spacing; Energy consumption; Frequency conversion; Frequency synthesizers; Interference; Phase locked loops; Transceivers; Voltage-controlled oscillators; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757439

Filename

757439