An all digital BiCMOS phase lock loop for VLSI processors

Author

Aun, Lim Chu ; Hasan, S. M Rezaul

Author_Institution

Intel Microelectron., Penang, Malaysia

fYear

1999

fDate

4-6 Mar 1999

Firstpage

318

Lastpage

320

Abstract

A BiCMOS all digital phase lock loop is described. This design is suitable for applications such as clock recovery and frequency synthesis in VLSI processors where thermal stability is an important factor. The main block of the design consists of a digitally controlled oscillator with wide frequency range and high thermal stability compared to CMOS design. An improved BiCMOS adder/subtractor was also implemented to reduce worst-case propagation delay-time. A small test chip was fabricated using MOSIS Orbit 2 μm low-cost analog CMOS process technology that provides lateral NPN bipolar device option

Keywords

BiCMOS digital integrated circuits; VLSI; circuit stability; digital phase locked loops; microprocessor chips; synchronisation; thermal stability; 2 micron; BiCMOS adder/subtractor; BiCMOS phase lock loop; VLSI processors; clock recovery; digital BiCMOS PLL; digitally controlled oscillator; frequency synthesis; thermal stability; worst-case propagation delay-time reduction; Adders; BiCMOS integrated circuits; Clocks; Digital control; Frequency synthesizers; Oscillators; Propagation delay; Thermal factors; Thermal stability; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on

Conference_Location

Ypsilanti, MI

ISSN

1066-1395

Print_ISBN

0-7695-0104-4

Type

conf

DOI

10.1109/GLSV.1999.757442

Filename

757442