• DocumentCode
    2704590
  • Title

    Context threading: a flexible and efficient dispatch technique for virtual machine interpreters

  • Author

    Berndl, Marc ; Vitale, Benjamin ; Zaleski, Mathew ; Brown, Angela Demke

  • Author_Institution
    Syst. Res. Lab., Toronto Univ., Ont., Canada
  • fYear
    2005
  • fDate
    20-23 March 2005
  • Firstpage
    15
  • Lastpage
    26
  • Abstract
    Direct-threaded interpreters use indirect branches to dispatch bytecodes, but deeply-pipelined architectures rely on branch prediction for performance. Due to the poor correlation between the virtual program´s control flow and the hardware program counter, which we call the context problem, direct threading´s indirect branches are poorly predicted by the hardware, limiting performance. Our dispatch technique, context threading, improves branch prediction and performance by aligning hardware and virtual machine state. Linear virtual instructions are dispatched with native calls and returns, aligning the hardware and virtual PC. Thus, sequential control flow is predicted by the hardware return stack. We convert virtual branching instructions to native branches, mobilizing the hardware´s branch prediction resources. We evaluate the impact of context threading on both branch prediction and performance using interpreters for Java and OCaml on the Pentium and PowerPC architectures. On the Pentium IV our technique reduces mean mispredicted branches by 95%. On the PowerPC, it reduces mean branch stall cycles by 75% for OCaml and 82% for Java. Due to reduced branch hazards, context threading reduces mean execution time by 25% for Java and by 19% and 37% for OCaml on the P4 and PPC970, respectively. We also combine context threading with a conservative inlining technique and find its performance comparable to that of selective inlining.
  • Keywords
    Java; computer architecture; instruction sets; multi-threading; program control structures; program interpreters; virtual machines; Java; OCaml; branch prediction; bytecodes; context threading; deeply-pipelined architectures; direct-threaded interpreters; dispatch technique; hardware program counter; linear virtual instructions; sequential control flow; virtual branching instructions; virtual machine interpreters; virtual program control flow; Algorithms; Computer languages; Context-aware services; Counting circuits; Debugging; Hardware; Hazards; Java; Pipelines; Virtual machining;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Code Generation and Optimization, 2005. CGO 2005. International Symposium on
  • Print_ISBN
    0-7695-2298-X
  • Type

    conf

  • DOI
    10.1109/CGO.2005.14
  • Filename
    1402073