DocumentCode
2705057
Title
Exploring scalability of FIR filter realizations on Graphics Processing Units
Author
Rebacz, Jeff ; Oruklu, Erdal ; Saniie, Jafar
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
fYear
2010
fDate
20-22 May 2010
Firstpage
1
Lastpage
5
Abstract
General-Purpose Computing on Graphics Processing Units (GPGPU) has lately been of great interest due to the release of architectures and software that simplifies programming graphics cards. This study explores how performance scales with FIR digital filters by varying the number of taps and the samples. We also discuss the trade-offs with various techniques for GPGPU programming in CUDA.
Keywords
FIR filters; computer graphic equipment; coprocessors; parallel architectures; parallel programming; CUDA; FIR digital filter; general-purpose computing; graphics processing unit; programming graphics card; software architecture; Finite impulse response filter; Graphics; Graphics processing unit; Instruction sets; Kernel; Programming; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Electro/Information Technology (EIT), 2010 IEEE International Conference on
Conference_Location
Normal, IL
ISSN
2154-0357
Print_ISBN
978-1-4244-6873-7
Type
conf
DOI
10.1109/EIT.2010.5612114
Filename
5612114
Link To Document