• DocumentCode
    2706421
  • Title

    Hardware annealing for fast retrieval of optimal solutions in Hopfield neural networks

  • Author

    Sheu, Bing J. ; Lee, Bang W. ; Chang, Chia-Fen

  • Author_Institution
    Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
  • fYear
    1991
  • fDate
    8-14 Jul 1991
  • Firstpage
    327
  • Abstract
    Due to the feedback characteristics of Hopfield networks, the solutions often get stuck at local minima where the objective functions have surrounding barriers. The theory and procedure of hardware annealing, which can retrieve the optimal solution in parallel, have been developed. In hardware annealing, voltage gains of output neurons in asynchronous VLSI neural chips are increased from an initial low value to a final high value in a continuous fashion. Hardware annealing can be applied to pure analog and mixed analog-digital neurocomputing systems. It achieves a speed-up factor of more than 10000 times over simulated annealing on a SUN-3/60 workstation
  • Keywords
    VLSI; mathematics computing; neural nets; simulated annealing; Hopfield neural networks; SUN-3/60 workstation; analog-digital neurocomputing; asynchronous VLSI neural chips; feedback characteristics; local minima; mathematics computing; objective functions; simulated annealing; Analog-digital conversion; Boltzmann distribution; Computational modeling; Hopfield neural networks; Intelligent networks; Neural network hardware; Neurons; Simulated annealing; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    0-7803-0164-1
  • Type

    conf

  • DOI
    10.1109/IJCNN.1991.155356
  • Filename
    155356