• DocumentCode
    2706652
  • Title

    A 10-bit 70 MS/s CMOS D/A converter

  • Author

    Nakamura, Yoshihiko ; Miki, T. ; Maeda, Atsushi ; Kondoh, H. ; Yazawa, Naoya

  • fYear
    1990
  • fDate
    7-9 June 1990
  • Firstpage
    57
  • Lastpage
    58
  • Abstract
    A 10-bit 70-MS/s D/A (digital-to-analog) converter fabricated in a 1-μm CMOS process is described. A linearity within ±0.5 LSB has been realized by a new switching sequence that is based on hierarchical error cancellation and suppresses both graded and symmetrical errors distributed in outputs of current sources. A layout technique for suppressing the influence of transistors implanted in tilt angles on linearity is also discussed
  • Keywords
    CMOS integrated circuits; VLSI; digital-analogue conversion; integrated circuit technology; 1 micron; 10 bit; 70 MHz; CMOS process; DAC; current source error suppression; digital-to-analog converter; hierarchical error cancellation; layout technique; linearity; switching sequence; transistors implanted in tilt angles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
  • Conference_Location
    Honolulu, Hawaii, USA
  • Type

    conf

  • DOI
    10.1109/VLSIC.1990.111093
  • Filename
    5727526
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2706652