• DocumentCode
    2706861
  • Title

    Wordline coupling noise reduction techniques for scaled DRAMs

  • Author

    Min, Dong-Sun ; Seo, Dong-Il ; You, Jehwan ; Cho, Sooin ; Chin, Daeje ; Park, Y.E.

  • fYear
    1990
  • fDate
    7-9 June 1990
  • Firstpage
    81
  • Lastpage
    82
  • Abstract
    The wordline architecture of the twisted word line (TWL) scheme and a wordline latch circuit for suppressing wordline coupling noise have been proposed and demonstrated. Using this approach, wordline coupling noise is reduced by 70% compared to the conventional wordline structure. This technique was found to be effective for suppressing wordline coupling noise with minimum layout penalty in scaled high-density DRAMs
  • Keywords
    DRAM chips; memory architecture; coupling noise reduction techniques; high-density DRAMs; minimum layout penalty; scaled DRAMs; twisted word line; wordline architecture; wordline latch circuit;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1990. Digest of Technical Papers., 1990 Symposium on
  • Conference_Location
    Honolulu, Hawaii, USA
  • Type

    conf

  • DOI
    10.1109/VLSIC.1990.111105
  • Filename
    5727538
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2706861