A current-mode column comparator circuit for high-speed, low-power on-chip cache-TAG memories

The authors describe a low-power comparator circuit which is especially useful for on-chip cache-TAG memories. A novel TAG memory comparator circuit scheme, called a current-mode column comparator (CMCC) scheme, is proposed, and the low-power nature of the CMCC without degraded accessing speed is described. An experimental 128-entry by 32-b TAG-memory test chip was fabricated using 0.5-μm BiCMOS technology, and a 3-ns address input to hit delay time was obtained. The power dissipation of the sense amplifiers was reduced by a factor of 10