Advanced 2D/3D ESD device simulation-a powerful tool already used in a pre-Si phase

Author

Esmark, K. ; Stadler, W. ; Wendel, M. ; Goßner, H. ; Guggenmos, X. ; Fichtner, W.

Author_Institution

Infineon Technol. AG, Munich, Germany

fYear

2000

fDate

26-28 Sept. 2000

Firstpage

420

Lastpage

429

Abstract

The tremendous advantages of adequate 2D/3D device simulations for ESD optimization are demonstrated. The pre-silicon ESD-protection concept of a new CMOS technology was completely based on high-current I-V characteristics simulated for different NMOS variations. Silicon verification proved the excellent simulation quality of the electrical behavior and, furthermore, of ESD thresholds.

Keywords

CMOS integrated circuits; MOSFET; circuit optimisation; circuit simulation; electric current; electrostatic discharge; integrated circuit modelling; protection; semiconductor device models; 2D ESD device simulation; 2D device simulation; 3D ESD device simulation; 3D device simulation; CMOS technology; ESD optimization; ESD thresholds; NMOS variations; electrical behavior; high-current I-V characteristics; pre-Si phase tool; pre-silicon ESD-protection concept; silicon verification; simulation quality; CMOS technology; Circuit simulation; Electrostatic discharge; MOS devices; MOSFETs; Predictive models; Protection; Robustness; Silicides; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000

Conference_Location

Anaheim, CA, USA

Print_ISBN

1-58537-018-5

Type

conf

DOI

10.1109/EOSESD.2000.890111

Filename

890111