A comprehensive analysis of breakdown mechanisms in 4H-SiC MOSFET and JFET

Author

Mihaila, A. ; Udrea, F. ; Amaratunga, G. ; Brezeanu, G.

Author_Institution

Dept. of Eng., Cambridge Univ., UK

Volume

1

fYear

2000

fDate

2000

Firstpage

185

Abstract

This paper presents a systematic analysis of breakdown mechanisms in silicon carbide MOSFET and JFET. For the MOSFET, the trench technology has been selected. The JFET structure is very similar to that having the distinctive feature of a buffer layer grown on the top of the drift region. Both devices are designed for 1.2 kV and were simulated and optimised using MEDICI and ISE TCAD software packages. This study indicates that the gate oxide breakdown puts a strong limitation on the electrical performance of the SiC trench MOSFET. Drawbacks encountered in SiC trench MOSFET, such as gate oxide breakdown, low channel mobility and the tight trade-off between the punch-through premature breakdown and the threshold voltage in the channel can be eliminated by using the SiC JFET

Keywords

MOSFET; isolation technology; junction gate field effect transistors; semiconductor device breakdown; semiconductor materials; silicon compounds; technology CAD (electronics); 1.2 kV; ISE; JFET; MEDICI; MOSFET; SiC; TCAD software packages; breakdown mechanisms; channel mobility; electrical performance; gate oxide breakdown; punch-through premature breakdown; threshold voltage; trench technology; Breakdown voltage; Buffer layers; Dielectric breakdown; Electric breakdown; MOSFET circuits; Photonic band gap; Semiconductor device breakdown; Silicon carbide; Threshold voltage; Wide band gap semiconductors;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 2000. CAS 2000 Proceedings. International

Conference_Location

Sinaia

Print_ISBN

0-7803-5885-6

Type

conf

DOI

10.1109/SMICND.2000.890214

Filename

890214