FPGA Implementation of a Multi-Level SPWM for Three-Level NPC Inverter

In this paper, a new circuit implementation of a multi-level sinusoidal pulse width modulation (SPWM) for three-level neutral point clamped (NPC) inverter is presented. The SPWM control scheme is realized with only a single FPGA chip LFEC10 from LATTICE, Inc. and the programming language is very high speed integrated circuit hardware description language (VHDL). The filed programmable gate array (FPGA) chip is incorporated in a digital signal processor (DSP) TMS320VC33. It receives the commands with specified amplitude, frequency, primary phase, min pulse width and dead time from DSP, and finishes the asymmetrical regular sampling principle of SPWM function independently. This circuit structure can provide an effective, flexible, and safe solution to high-power inverters. The output gating signals of the proposed circuit are used to control the inverters of the drive system of a 6 kV/1000 kW motor. The simulation and experimental results are given to verify the implemented SPWM control system