A test chip for interconnect capacitance modelling in a CMOS process

Based on our previous works on On-Chip measurement of small capacitances, we present a Test Chip to provide experimental data for measurement and modelling of wiring capacitances of a CMOS Process. Patterns include line-to-line capacitance (for the two metal layers and the polysilicon layer), inter-layer capacitance (extraction of both area and perimeter terms of the capacitance for each couple of layer), matching (relative scattering between two identical devices), crossover (capacitance between two crossing lines) and other parameters generally used when extracting parasitic elements from an electronic design